Hot Carrier Effect Paper Summary and Discussions

The integrity of gate oxide is greatly affected by the continued accumulation of scale deeper into the sub-micrometer regime of a device. Breakdown of the gate oxide, process-induced damage, and hot-carrier injection is among the most critical reliable issues associated with scaling accumulation (Kwon, Kim & Kim, 2019). Introduction of charge carriers with high energy content through high-energy protons or high electric fields of high-energy photons into the gate oxide is capable of causing microscopic change on the structure, which may result in the creation of defects (Cristoloveanu, 1997). The defect sites trap some charges which induce permanent parametric drift eventually resulting in degradation of the device's performance as well as circuit failure (Song et al., 2013). The condition can be corrected using a variety of strategies including gate oxide chemical modification by Cl, N, and F incorporation. 

Tungsten polycidation significantly affects the reliability of the hot-carrier variously particularly the n- and p-MOSFET's . There is predominant degradation of n-MOSFET's by 

the generation of interface state; the trap generation can be immune by replacing the Si-H bonds with more strong bonds of Si-F resulting within Si-SiO interfaces. In as much as n-MOSFET require frequent reliability enhancement, the p-MOSFET's immunity in hot carriers can still be severely degraded by the WF-based CVD tungsten polycidation (Kwon, Kim & Kim, 2019). The measurement of gate-to-drain capacitance is often used to quantitatively compare the effectiveness of oxide trap charges in these two devices. 

The rapid trapping of electrons within the WSi devices in the initial state can be associated with increased F-related traps resulting from Si-O bonds breaking in the process of polycidation by the atoms of F present in the bulk of oxide (Saha, Varghese & Mahapatra, 2006). There is also a significant drop in the rate of electron de-trapping for the samples of WSi. Coupling the increase in the concentration of traps of electron brought about by F with reduced field-induced detrapping results in a significant decrease in the lifetime of dc hot-carriers over four magnitude orders under normal voltages of operation depending on the criterion of ∆Vt = 50V (Cristoloveanu, 1997). The efficiency of WF-based silicidation for the CMOS devices' deep sub-micrometer may be overwhelmed by the increasingly essential function of the effects of hot-carriers within p-MOSFET's in the lifetime of the CMOS circuit. 

Hot Carrier Injection Mechanisms 

Generally, ``hot carriers'' refer to particles that acquire kinetic energy of high intensity after being speed up by an extremely high electric field (Song et al., 2013). The carriers of energy can then be injected into the device's regions that are normally forbidden, including the gate dielectric, into which they may be trapped or become states of an interface to be generated (Saha, Varghese & Mahapatra, 2006). Such defects may ultimately result in the shifts of threshold voltage as well as MOS devices' trans-conductance degradation. In an attempt of preventing, or minimizing the carrier degradation at the least, a variety of design modifications of the devices can be done (Song et al., 2013). These may include a larger length of the channel and double diffusion of the drain as well as sources. 

Hot carrier injections into the dielectrics involve four different mechanisms as discussed below. Figure 1 shows a general overview of the discussed injection mechanisms. 

Figure 1: Hot Carrier Injection 

Channel Hot-Electron Injection (CHE) 

CHE injection attains its maximum when the gate voltage and the drain voltage are approximately equal. Figure 2 below brings this condition out clearly as ``lucky electrons'' that are deflected towards the increased gate voltages tend to acquire sufficient electrical energies from the surrounding channel field thus surmounting the barrier of Si/SiO2 around the channel's drain end (Khurgin, 2020). Measurements of CHE injection is recorded as gate current at a maximum around the point Vgs ≈ Vds. the field attracts no gate electrons where gate voltages are lower (Song et al., 2013). The impact of injection of hot electrons, hot holes, and ionization at higher drain causes these drain fields to cause multiplication of avalanche as a result of impact ionization thus reducing the gate current measured. 

Figure 2: Channel Hot-Electron Injection 

The figure shows the condition at which CHE is in stress where the ``lucky electrons'' acquire energy that is sufficient as they cross the channel before their injection into the dielectric to cause a gate current together with the interface and hence the degeneration of oxide (Saha, Varghese & Mahapatra, 2006). The electric field of the oxide is identical to that of the measurement technique of drain pulsed voltage. 

Drain Avalanche Hot-Carrier Injection (DAHC) 

The DAHC injection becomes significant at the conditions in which the stress has high Vds but lower Vgs. This is brought when the electrons, as well as holes generated by the multiplication of avalanche, are injected (Song et al., 2013). The content of energy that is gained by the carriers’ results from the higher electric field existing in those drain regions. 

Figure 3: Drain Avalanche Hot-Carrier Injection 

Figure 3 clearly depicts the fact that hot carriers contributes to effective ionization which generates electron-hole pairs. The hot holes as well as hot electrons within the DAHC regime undergo direct injection into the dielectric. Base on the data obtained experimentally, it is evident that DAHC effect is more responsible for the degradation of devices related to hot carrier compared to the effect of hot-electrons in the channel. 

Secondarily Generated Hot-Electron Injection 

Figure 3 clearly depicts the fact that hot carriers contribute to effective ionization which generates electron-hole pairs. The hot holes, as well as hot electrons within the DAHC regime, undergo direct injection into the dielectric. Base on the data obtained experimentally, it is evident that the DAHC effect is more responsible for the degradation of devices related to hot carriers compared to the effect of hot-electrons in the channel. 

Secondarily Generated Hot-Electron Injection 

SGHE injection is a process generated by photon induction at the start. The generation of photons occurs in higher field region close to the drain where they induce an electron-hole pair's generation process (Saha, Varghese & Mahapatra, 2006). The avalanche multiplication impacts follow close to the drain region which leads to the electrons as well as holes injection into those dielectrics. This activity is sustained by substrate bias that adds to the compulsion of the hot carriers towards interfaces. The SCHC has been proved to cause a significant amount of threshold shift, which occurs even in the bias conditions where the VD<3V. 

Substrate Hot-Electron/Hole Injection 

SHE/SHH injection results from a high negative/positive bias that occurs towards the back of substrate Vsub. This drives the carriers within the substrate towards the Si/SiO2 interfaces thus gaining excessive kinetic energy on the depletion surfaces. The substrate carriers may be generated either by optically electrically by p-n injection (Khurgin, 2020). The carriers may consequently overcome the existing interface energy barrier and may, therefore, be injected into the gate oxide. 

In most occasions, SHE/SHH is applied in insulator reliability and quality test investigations (Saha, Varghese & Mahapatra, 2006). Its major advantage is the uniform distribution of the interface carriers that are energetic at the interface along the channel as opposed to the mechanisms of the injection that has earlier been described, in which the injection maximum occurred near the drain channel's end (Saha, Varghese & Mahapatra, 2006). This means the proper definition of the conditions of stress at the interface. In the process of pinning the surface potential Øsurf, the field of oxide is singly dictated by the gate voltage. The substrate voltage is used in the determination of the potential decrease in the substrate. In that case, a variety of important conditions such as the carrier energy, oxide field as well as the current intensity is capable of being adjusted independently. 

Conclusion 

The efficiency of WF-based silicidation for the CMOS devices’ deep sub-micrometer may be overwhelmed by the increasingly essential function of the effects of hot-carriers within p-MOSFET's in the lifetime of the CMOS circuit. In an attempt of preventing, or minimizing the carrier degradation at the least, a variety of design modifications of the devices are always done. 

References 

Cristoloveanu, S. (1997). Hot-carrier degradation mechanisms in silicon-On-Insulator MOSFETS. Microelectronics Reliability, 37(7), 1003-1013. doi: 10.1016/s0026-2714(96)00262-4 

Khurgin, J. (2020). Fundamental limits of hot carrier injection from metal in nanoplasmonics. Nanophotonics, 9(2), 453-471. doi: 10.1515/nanoph-2019-0396 

Kwon, H., Kim, D., & Kim, T. (2019). Hot carrier instability associated with hot carrier injection and charge injection in In0.7Ga0.3As MOSFETs with high-κ stacks. Japanese Journal Of Applied Physics, 58(11), 110906. doi: 10.7567/1347-4065/ab4ad4 

Saha, D., Varghese, D., & Mahapatra, S. (2006). Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stress. IEEE Electron Device Letters, 27(7), 585-587. doi: 10.1109/led.2006.876310 

Song, Z., Chen, Z., Yong, A., Song, Y., Wu, J. and Chien, K., 2013. The Failure Mechanism Worst Stress Condition for Hot Carrier Injection of NMOS. ECS Transactions, 52(1), pp.947-952.