The 5nm Transistor: The Future of Computing

The November 16th, 1904 invention of the vacuum tube was the humble beginning of the modern-day transistor. The first working transistors were developed at Bell Labs by William Shockley, John Bardeen, and Walter Brattain in 1948. The metal-oxide-semiconductor field-effect transistor (MOSFET) was later developed by Dawon Kahng and Mohamed Atalla in 1959. The production of the MOSFET transistor enabled mass production for a wide range of uses. This type of transistor had a much lower power consumption, high scalability, and a higher density. The MOSFET enabled manufacturers to produce high-density integrated circuits. The mass production of the MOSFET transistors revolutionized the electronics industry. It became the most common type of transistor with uses in communications technology, electronics and computers. Billions of MOS transistors are produced every day. Since the invention of the transistor, the race towards more efficient and less power-hungry transistors has pushed innovation to the edge of a technologically tomorrow. IBM has, therefore, taken the opportunity to research a new 5 nanometer transistors. The applications of this transistor will be revolutionary by offering fast performance while being highly power efficient. Devices like phones, laptops, wearable gear, and even medical equipment will significantly improve based on the development of this new transistor. Research into improving the transistor is an excellent step towards achieving improved power efficiency and battery life. The demand for the internet of things, AI, machine learning, autonomous vehicles is growing fast and is a driving force scaling down the current 10nm and 7nm nodes for superior performance. 

The 5nm Transistor 

The 5nm transistor was announced in the 2017 Symposia in Kyoto, Japan. The breakthrough was achieved through the alliance of IBM, Samsung, and GLOBALFOUNDRIES (Bu, 2017). To achieve this feat, they had to change how chip elements are arranged. Layers of silicon nanosheets are stacked horizontally in a 5nm transistor while in previous models they were stacked vertically. This new architecture opened a fourth gate on the transistor that allowed electrical signals to through and between other transistors on a chip. The signals can pass through a switch that is less than the width of 2 or 3 DNA strands. (Bu, 2017). The 5nm lithography process is a node semiconductor making process after the 7nm node. 

The term does not represent any geometry of the transistor but is simply a brand name. The process technology in 5nm nodes features the use of FinFet transistors with denset metal pitches in 30s of nanometers and fin pitches in the 20s of nanometer. It will be able to make extensive use of extreme ultraviolet (EUV) for the crucial dimensions because of its small size (Lapedus, 2019). The 5nm node has silicon densities between 130-230 million transistors per square millimeter in regard to raw cell density. 

Moore’s law on emerging trends in the semiconductor industry has been the Achilles heel of chip manufacturing. However, over the past few years, there have been a likely impending end to this exponential function as the transistors have become smaller. Therefore, the power needed to cool the chips is reduced in direct proportion with the development of even smaller chips (Theis & Wong, 2017). When a transistor can conduct electrical signals faster, the microchip can process them faster and thereby increasing efficiency. The 5-nanometer transistors hold tremendous promise and are bound to be even better over the next few years as development continues. 

Since the invention of the integrated circuit over sixty years ago, manufactures of computer chips have managed to pack more transistors onto a single piece of silicon every year. Moore, in 1965, observed that transistor density doubled every twenty-four months. He predicted that this trend will continue (Theis & Wong, 2017). His prediction was true for a remarkable forty years. His law, however, became defunct over a decade ago. In 1960, a standard integrated circuit had ten transistors. Today, complex silicon chips have up to 10 billion transistors. This means they can hold a billion times more transistors. The original observation of doubling every one year now takes three years. Similar slowing has been experienced in performance improvements. Power was of little influence during the introduction of transistors. Battery-hungry devices, however, have made power a significant component of the technology. (Rashid, 2016). The only element that has kept a similar pace to Moore’s law over the last 50 years is the cost per transistor. 

Recommendations 

Early preliminary results show a marked improvement of about fifteen percent in efficiency and about thirty percent in power efficiency. The marked improvement will boost the growth and development of artificial intelligence through improved cognitive computing. The data-intensive processes will significantly benefit from the faster and highly efficient chips based on these transistors. The recent breakthrough based on the stacking of nano-sheets in place of the typical FinFet architecture in the fashioning of the transistor has been hailed as a great start of the 5nm technology (Loubet et al., 2017). The horizontal stacking of gate-all-around (GAA) Nanosheet structure can provide the basis of further development as the architecture has delivered the logic device needs. Its adaptable design has also proved to be more straightforward with greater electrostatics and dynamic processing performance. 

By being among the leaders in the development of better transistors, IBM can reap great benefits not only from sales but also by leading the world into a new greener world. (Asenov et al., 2016). Electronic waste will be less as batteries will last longer and even require less raw materials to manufacture. Industries that require great processing power will save on their energy costs and thereby lower their overhead costs. 

The development of 5-nanometer, the 3nm, and the 2nm transistors is the future of computing. The impact of the architecture on devices and applications will be huge and span across all industries. The primary benefits of increased performance and power efficiency will lead to the transistor's adoption into various fields that we could never have thought about before. The innovation will push the limitations of the current transistors and help eke out the much-needed additional performance (Asenov et al., 2016). Therefore, IBM needs to lead the efforts in the research and development of the improved transistor. 

More ways to send a signal through this transistor translates to a 40% performance enhancement over the 10nm chips while using a similar amount of power. More ways to send a signal also equates to 75% power saving at a similar performance level. To put this into perspective, if your mobile device with 10nm chips has 10% power left, it would probably take minutes to go off but the same amount of power will last hours with the 5nm transistors (Bu, 2017). A future 5nm chip powered mobile will last many days longer than the current version. 

The current vertical fin transistors power the 14nm, 10nm, and the 7nm chip. The vertical fin is a has a third dimension and allows for 3 gates for efficiency and improved power. The previous versions were two-dimensional planar chips (Bu, 2017). The 5nm transistors will take years to find their way in commercially used devices, but their announcement remains a milestone. TSMC and Samsung began limited risk production of the 5nm nodes in 2019 and mass production was slated for 2020. The technology is yet to be commercialized. 

Chips created using the 5nm transistors could potentially achieve big performance in mobile devices and CPUs. There is a predicted challenge in terms of heating. High-performance chips produce a lot of heat and require bulky and expensive cooling techniques (Al-Ameri, 2017). While it will considerably save on power, it might require an enhanced PC cooling system. Research in other materials seems to provide the answer to this challenge. Metal vanadium oxide has been shown to conduct electricity without conducting heat. This could see radical changes in how PC components are built. This could offset the heating problem caused by 5nm transistor chips. 

From an economic point of view, few organizations can afford high-performance silicon chips but the technology is needed. Their production and supply have slowed a bit but their use is required. Leading-edge chips are crucial in modern smartphones and servers. The ability to compute ten-times faster than the current rate will be competitively required and commercially useful in the near future even for non-technical niches. Deep learning’s accomplishments are a testament to that (Lapedus, 2019). There is no end in sight for the demand for technological advancements for enhanced computing power. The 5nm transistor chips are at the center of such advancements in computing power and power saving. 

The Samsung 5nm nodes that provide up to twenty-five percent increase in logic area with a ten percent higher performance or twenty percent lower power is expected to be rolled out in 2020. TSMC is about to begin mass production of the 5nm based chips (Vora et al., 2016). It will be the second one to use ultraviolet lithography process technology and the benefits of the smaller node cannot be overemphasized. It has reduced power consumption and increased transistor density. 

In mobile devices, 5nm technology is a welcome advancement. It could have major implications for the future performance of these devices. The size of these gadgets, for one, could dramatically reduce. Shrinking the process node from 10nm and 7nm to 5nm translates to a leap forward in terms of the size of transistors on the chip. The 5nm transistors are also expected to significantly increase the speed and efficiency of the chips. The advancement allows for the use of more transistors. An A14 iPhone chip could pack as many as 80 percent more transistors than the A13 used in iPhone 11. MacWorld’s expectation of Apple could result in up to 15 billion transistors in its new chip. The next-generation iPhone could achieve the same efficiency and speed as some of Apple’s top MacBooks (Martindale, 2020). A migration to 5nm would herald an exciting step toward bringing super powerful and efficient processors in the market. 

From the 22nm transistor to the 7nm transistor, FinFets have enjoyed success and the outcome for scaling one more node is greatly awaited. The stack of horizontal nanowire as opposed to the current vertical architecture has opened a fourth gate (Lapedus, 2019). The 5nm gate-all-around transistor is expected to achieve good electrostatic property. 

All new technologies are faced with new challenges and the 5nm transistor chip is not immune from this. However, there are ways to overcome the foreseen challenges of this futuristic transistor technology. The outcome of reducing the body thickness is lower mobility as surface roughness scattering increases. The leakage problem also increases as the FinFet transistor size is scaled down further. This results in threshold flattening and overheating. Using new effective materials is the solution to these challenges. Such materials include the carbon nano tube FET (CNTFET), The gate-all-around FET (GAAFET), and compound semiconductors such as indium gallium arsenide (Vora et al., 2016). These methods provide first-rate properties of motilities, heat dissipation, and offer high current carrying capability. 

Conclusion 

The need for more powerful transistor chips will not run out as the world enters a new era of computing. The demand for the internet of things, AI, machine learning, autonomous vehicles is growing fast and is a driving force scaling down the current 10nm and 7nm nodes for superior performance. A global rollout of the 5G technology will be complemented greatly by a similar deployment of 5nm chips. Even if it is in the early application stages, the 5nm is a much-needed performance improvement component that is needed now if not later. 

References 

Al-Ameri, T., Vihar p. G., Fikru A and Asenov, A. (2017). Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications. Journal of the Electron Devices Society . https://core.ac.uk/download/pdf/96883875.pdf 

Asenov, A., Wang, Y., Cheng, B., Wang, X., Asenov, P., Al-Ameri, T., & Georgiev, V. P. (2016). Nanowire transistor solutions for 5nm and beyond. 2016 17th International Symposium on Quality Electronic Design (ISQED), 269–274. 

Bu, H. (2017). 5 nanometer transistors inching their way into chips. IBM . https://www.ibm.com/blogs/think/2017/06/5-nanometer-transistors/ 

Lapedus, M. (2019). 5nm Vs. 3nm. Semi-engineering . https://semiengineering.com/5nm-vs-3nm/ 

Loubet, N., Hook, T., Montanini, P., Yeung, C.-W., Kanakasabapathy, S., Guillom, M., Yamashita, T., Zhang, J., Miao, X., Wang, J., Young, A., Chao, R., Kang, M., Liu, Z., Fan, S., Hamieh, B., Sieg, S., Mignot, Y., Xu, W., … Khare, M. (2017). Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, T230–T231 . https://doi.org/10.23919/VLSIT.2017.7998183 

Martindale, J. (2020). Here’s why a 5nm iPhone A14 chip would be such a big deal. Digital Trends. https://www.digitaltrends.com/computing/5nm-iphones-herald-super-faster/ 

Rashid, S. (2016). Moore’s law effect on transistors evolution. International Journal of Computer Applications Technology and Research . Volume 5 issue 7, 495 – 499. https://ijcat.com/archives/volume5/issue7/ijcatr05071014.pdf 

Theis, T. N., & Wong, H.-S. P. (2017). The end of moore’s law: A new beginning for information technology. Computing in Science & Engineering , 19(2), 41–50. 

Vora, P., Verma, A., Parikh, D. (2016). Futuristic Transistor Technology below 5nm node. Ruben Reyes . https://rubenreyes.com/articles/Futuristic_Transistor_Technology_below_5nm_node.pdf 

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